The present invention relates to the field of communications between devices in a processor-based system and more particularly, to buses for communication between devices.
Data buses are found in virtually all computers and processor-based devices, serving to interconnect a processor to random access memory, or to enable communications between a processor and an application-specific integrated circuit (ASIC) or peripheral devices, as examples. Some of these data buses are single wire buses. Conventionally, single wire buses that support communication between multiple devices use a wired-or technique. Typically, the bus is held high by a pull-up resistor or other current source. When a device wishes to use the bus for communication, the bus is actually driven low. Single wire buses are usually used to transfer data between devices or to send a clock signal.
In some cases, devices operating on the same bus may be capable of operating at different speeds. In some systems devices simply start out at a slow speed and negotiate to a higher speed if possible. This may be ineffective because communication necessarily progresses at a speed which may be slower than either device is capable of operating at. More complex system may require complex negotiations to set the bus speed.
Thus, there is a need for a bus negotiation scheme which automatically adjusts the bus speed to accommodate for the communication capabilities of the devices coupled to the bus.
In addition, bus systems may have elaborate arbitration schemes for controlling access to the bus when more than one bus agent seeks to use the bus at one time. These schemes complicate bus operation and limit access to such a bus by bus agents with relatively limited resources.
Thus, there is also a need for improved ways of negotiating bus access.